Moving Average Dsp

Verfeinern Sie DSP Firmen und Produkte: Klicken Sie auf irgendeinen Verkäufer, um eine Auflistung der DSP verwandten Produkte zu sehen. Die FMC645 ist eine digitale Signalprozessor-FMC-Tochterkarte, die auf dem Texas Instruments TMS320C6455 Gerät basiert. Die FMC645-Tochterkarte ist mechanisch und elektrisch konform mit dem FMC-Standard (ANSIVITA 57.1). Die Karte hat einen Steckverbinder mit hohem Stift und kann in einer leitungsgekühlten Umgebung eingesetzt werden. Die Karte ist mit Stromversorgung und Temperaturüberwachung ausgestattet und bietet mehrere Power-Down-Modi zum Ausschalten von unbenutzten Funktionen und Peripherie-Schnittstellen. Mehrere Gigabit-Differentialpaare vom FMC-Stecker werden verwendet, um eine PCIe - und Serial Rapid IO-Schnittstelle zwischen dem FMC und dem Carrier zu implementieren. Viele andere digitale IO-Schnittstellen werden dem FMC-Carrier auch zur Verfügung gestellt. Durch den Einsatz von Level-Übersetzern zwischen dem DSP und dem FMC-Stecker kann der FMC645 auf jedem VITA 57.1-kompatiblen Träger voll betrieben werden. Eine 512 MB DDR2 SDRAM On-Board-Bank verbindet sich direkt mit dem DSP und stellt so dem FMC645 die für anspruchsvolle Signalverarbeitungsanwendungen benötigten Speicherressourcen zur Verfügung. () FM577Die FM577 ist eine kostengünstige, leistungsstarke 65nm FPGA-basierte Platine im PMC-Formfaktor () FM485Dual FPGA Virtex-5 und Virtex-4 mit 128 MB DDR2 und 16 MB QDRII SDRAM Local Memory PMC-X Und XMC für High-Bandbreite Analog-Umwandlung DSP-Verarbeitung () FM486Dual FPGA Virtex-5 Virtex-4 mit bis zu 512 MB DDR3 und 8 MB QDRII SDRAM Lokaler Speicher PMC-X und XMC für High-Bandbreite Analog-Umwandlung DSP-Verarbeitung () FM482Dual Xilinx Virtex-4 FPGA Signalprozessor PMCXMC () Ein DSP DAC für Hochgeschwindigkeits-Analogsignal Regeneration und digitale Signalverarbeitung () Ein DSP ADC für Hochgeschwindigkeits-Analogsignalaufnahme und digitale Signalverarbeitung () CPCI381A 3U CompactPCI Board bietet eine leistungsstarke Plattform Für Hochgeschwindigkeits-Analog-Signal-Capture und Digitale Signalverarbeitung () TMS320C32 Fließkomma DSP, läuft bei 60 MHz, liefert 30 MIPS Zwei simultane Abtastung 12-Bit AD Kanäle Programmierbare Abtastrate bis zu 7,5 Msamplessec Bietet eine leistungsstarke Plattform für High-Speed-Analog Signalaufnahme und Digitalsignalverarbeitung () Zwei analoge Eingangskanäle können gleichzeitig (maximal) 7,5 MSps Abtastrate abtasten. Lokale Software ermöglicht verbesserte und anwenderspezifische Signalverarbeitung Gain - und Offsetfehler werden durch die DSP CPCI383A 3U CompactPCI Board kompensiert Leistungsstarke Plattform für Hochgeschwindigkeits-Analogsignal (Re-) Erzeugung und digitale Signalverarbeitung () TMS320C32 Gleitkomma DSP, läuft bei 60 MHz und liefert 30 MIPS Drei Hochgeschwindigkeits-16-Bit-DA-Kanäle Analogausgangsrate ist programmierbar bis 7,5 Msamplessec (mit DMA, Single Channel) Bietet eine leistungsstarke Plattform für die Hochgeschwindigkeits-Analogsignal - (Re-) Erzeugung und digitale Signalverarbeitung () Analog und digital IO () Analog und Digital IO () Der M393 8-Kanal Differentialeingang ADC M - Modul ist sehr gut geeignet, um in Anwendungen eingesetzt zu werden, in denen autonome Signalumwandlung ein Thema ist, sowie in Standard-Midrange-Anwendungen () Aktivierte Kanäle werden mit maximaler Geschwindigkeit gescannt und Umwandlungsergebnisse werden im Shared Memory gespeichert. Ein lokaler DSP führt alle aus Funktionalität und benutzerspezifische Funktionen können für den kundenspezifischen Betrieb hinzugefügt werden. Das M392 16-Kanal-Common-Mode-Eingang ADC M-Modul eignet sich hervorragend für Anwendungen, bei denen eine autonome Signalumwandlung ein Problem ist, sowie in Standard-Midrange-Anwendungen (). Aktivierte Kanäle werden mit maximaler Geschwindigkeit gescannt Umwandlungsergebnisse werden im Shared Memory gespeichert. Ein lokaler DSP führt alle Funktionalitäten wie Kalibrierung durch. Benutzerspezifische Funktionen können für den kundenspezifischen Betrieb hinzugefügt werden. TMS320C32 Fließkomma DSP, läuft bei 60 MHz, bietet 30 MIPS () Optimiert für niedrige Kosten und erweitert die Reichweite von FPGAs weiter in kostensensible, hochvolumige Anwendungen () Kundendefinierte Feature-Set, branchenführende Performance und Low Leistungsverbrauch Stark erhöhte Dichte und mehr Features, alle zu deutlich niedrigeren Kosten 150 eingebettete 18 x 18 Multiplikatoren Nios II, StratixInternale Taktfrequenzraten bis 500 MHz und typische Leistung 250 MHz () liefern im Durchschnitt 50 schnellere Leistung und mehr als 2x die Logik Kapazität als erste Generation Stratix FPGAs liefern 50x höhere Multiplikatorbandbreite als Single-Chip, eigenständige digitale Signalprozessoren Die DSP-Blöcke haben die Flexibilität und Leistung, um schnelle, arithmetisch-intensive Anwendungen wie Bildverarbeitung, drahtlose Kommunikation, Militär, Rundfunk und Medizinische 28-nm Stratix V FPGAs Mit dem variablen Präzisions-DSP-Block kann Alteras Stratix V FPGA 8211 auf einer Block-by-Block-Basis 8211 verschiedene Präzisionen von 9-Bit x 9-Bit bis zu einem präzisen Gleitkomma (Mantisse) unterstützen Multiplikation) innerhalb eines einzigen DSP-Bausteins () Damit werden Sie von FPGA-Architektur-Einschränkungen befreit, so dass Sie die optimale Präzision in jeder Phase des DSP-Datenpfades nutzen können. Erhöhte Systemleistung, reduzierter Stromverbrauch und reduzierte architektonische Einschränkungen Jeder Variable-Präzisions-Block kann Zur Kompilierzeit konfiguriert werden: Dual 18-Bit x 18-Bit Multiplikatoren in der Summe oder unabhängige Modi Bis zu 680K Logik-Elemente (LEs) 2X größer als Alteras Stratix III Familie Altera 40-nm-Geräte erfüllen die vielfältige High-End-Anwendung Braucht in einer Vielzahl von Märkten wie drahtloser und drahtgebundener Kommunikation, Militär-, Rundfunk - und ASIC-Prototyping Stratix DSP Development KitA Entwicklungskit für Texas Instruments DSP-Entwicklungsplattformen zur Entwicklung von FPGA-Coprozessoren () Ermöglicht eine Entwicklungsplatine mit dem Stratix EP1S80-Gerät , Zwei 12-Bit-, 125-MHz-AD-Wandler, zwei 14-Bit-, 165-MHz-DA-Wandler, 64 Mbits Flash-Speicher, 2 Mbyte Synchron-SRAM und ein Anschluss an Analog Devices AD-Evaluierungskarten Inklusive einer plattformübergreifenden Tochterkarte Das direkt in Texas Instruments Hochleistungs-TMS320C6000 und kostengünstige TMS320C5000 DSP-Entwicklungsplattformen einsetzt Bietet Hardware-Evaluierungsversionen von Schlüssel-DSP-geistigem Eigentum, einschließlich eines FIR-Compilers, unendlicher Impulsantwort (IIR) Filter-Compiler, sowie Correlator, FFT, Viterbi , Und Reed Solomon Kerne Stratix II FPGAExtensive IP-Portfoliounterstützung () DSP-Blöcke bieten höhere Leistung mit Multiplikator, Pipeline und sammeln etwas fehlt hier bietet mehr als 142 GMACS von DSP-Durchsatz über DSP-Blöcke liefert 4x die DSP-Blockbandbreite von Stratix-Geräten 8211 nach oben Bis 370 MHz Ein DSP-Entwicklungswerkzeug mit erweitertem Zugriff auf Altera IP und Unterstützung für die MathWorks MATLAB 7SimuLink 6 Software () Unterstützt die Atratix II und Cyclone II Gerätefamilien Unterstützt Alteras DSP MegaCore IP Portfolio Enthält einen Farbraumwandler UP Kern und eine Kantenerkennung Referenzdesign mit einem zweidimensionalen Filter für Video - und Bildverarbeitungs-Designs Hochgeschwindigkeits-IO-Signalisierung und Schnittstellen () Unterstützt die neuesten externen Speicher-Schnittstellen in dedizierten Schaltungen, einschließlich DDR2 SDRAM, RLDRAM II und QDRII SRAM-Geräte bringt programmierbare Logik-Funktionalität und Vorteile Zu neuen Anwendungen, die Design-Sicherheit erfordern TriMatrix Memory Stratix EP1S80A DSP-Entwicklungsplatine () Im Lieferumfang des Stratix Professional Edition enthalten DSP-Entwicklungskits Zwei 12-Bit-, 125-MHz-AD-Wandler Zwei 14-Bit-, 165-MHz-DA-Wandler Links MATLABSimulink-Tools mit dem Altera Quartus II-Design-Software () Unterstützt Manda-DSP-IP Unterstützt Stratix-, Stratix II-, Cyclone - und Cyclone-II-Familien Ermöglicht das Rapid-Prototyping mit den DSP-Entwicklungskarten von Alterathird-Party Stratix II Dev. KitDSP-Entwicklungsplatine, Stratix II Edition mit einem Statix ​​II-Gerät () Bietet eine Vielzahl von analogen und digitalen IOs 16 MB SDR SDRAM 16 MB Flash 1 MB SRAM 32 MB kompakte Flash-Speicher MATLABSimulink Evaluierungssoftware DSP BuilderLinks MATLABSimulink-Tools mit der Designa-Software Altera Quartus II () Völlig unterstützt Altera DSP IP Unterstützt Stratix, Stratix II, Cyclone und Cyclone II Familien Ermöglicht Rapid Prototyping mit Alterathird-Party DSP Entwicklungsboards Cyclone II FPGAIndustrys kostengünstig programmierbare Logikplattform für DSP-Implementierung () bietet bis zu 68.416 LEs Logik an Dichte und 1,1 Mb eingebetteten Speicher liefert eingebettete konfigurierbare Multiplikatoren für kostengünstige DSP-Anwendungen Bietet bis zu 150 18-Bit x 18-Bit Multiplikatoren mit bis zu 250 MHz Ein Single-Chip-Mikrocomputer für die digitale Signalverarbeitung und andere High-Speed ​​optimiert Numerische Verarbeitungsanwendungen () Das EZ-KIT Lite-Auswertungskit ist für ADIs ADSP-21160x SHARC-Familie von DSPs sowie die ADSP-2189 M-Serie () verfügbar. Es bietet eine kostengünstige Methode zur Erstbewertung dieser beiden DSP-Architekturen Das ADSP-21160M EZ-Kit Lite Kit besteht aus dem ADIs VisualDSP Toolset Das ADSP-2189M EZ-KIT Lite Kit besteht aus einer eigenständigen DSP-Karte mit Codegenerierung und Debug-Software und erleichtert die Auswertung der ADSP-218x DSP - Sowie die VisualDSP-Entwicklungsumgebung, die einen C-Compiler, Assembler und Linker enthält. Ein 16-Bit-Fixpunkt-DSP, optimiert für Telekommunikation und andere Hochgeschwindigkeits-numerische Verarbeitungsanwendungen () Betrieb bei 160 MHz und ist in der Lage, 160 MIPS DSP ist Code kompatibel mit der Familie ADSP-21xx mit erhöhter Leistung On-Chip-System-Schnittstellen unterstützen T1, E1 und H.100-basierte Hochgeschwindigkeits-Telefonsysteme Ein leistungsstarker DSP, der in der Lage ist, MCU-Steuerungsfunktionalität in einem einzigen Befehlssatz mit einer Leistung von 300 MHz zu liefern () Ein eingebetteter DSP-Prozessor, der zwei identische Blackfin-DSP-Kerne () Ermöglicht symmetrisches Multiprocessing (SMP) Leistung von 750 MHz und 1500 MMACs (Millionen mehrfache Akkumulationsoperationen) pro Kern Jeder Kern enthält zwei Multiplikatorakkumulatoren (MACs), zwei 40-Bit-ALUs, vier 8-Bit-Video-ALUs und einen einzigen Fassschieber Ein Internet Gateway-Prozessor DSP-Chip mit einer Architektur, die mehrere Operationen parallel durchführen kann () Ein Satz von drei DSP-Prozessoren in der TigerSHARC-Familie () Ein TigerSHARC DSP-Prozessor () Statische superskalare Architektur, die 1, 9, 16 und 32-Bit-feste unterstützt Punkt-Verarbeitung Hochleistungs-600-MHz, 1,67 nsecs Befehlsrate DSP-Kern 24 Mbits On-Chip-Embedded-DRAM intern organisiert in sechs Bänken mit benutzerdefinierter Partitionierung Ein 16-Bit-Fixpunkt-DSP, optimiert für Telekommunikation und andere High-Speed-Numerik Verarbeitungsanwendungen () Eine Familie von sechs Single-Chip-Mikrocomputern, optimiert für digitale Signalverarbeitungsanwendungen () Ein 100 MHz SIMD 32-Bit-Fixpunkt - und Gleitkomma-DSP () 1-Mbit Dual-Port, Onchip SRAM kann Benutzer sein Konfiguriert IEEE 784-884 Gleitkomma-konform 14 DMA-Controller-Kanäle unterstützen Datenübertragung zwischen internem Speicher und externem Speicher, externen Peripheriegeräten, Host-Prozessor und mehreren Ports SHARC174 Prozessoren kombinieren in ihrer dritten Generation einen leistungsstarken Fest - und Floating - Punkt-Verarbeitung Kern mit anspruchsvolle Speicher und IO-Verarbeitung Subsysteme. () Hochleistungs-Single-Multiply-Accumulate (MAC), 16-Bit-Fixpunkt-DSP-Kern, der speziell für eingebettete und hochintegrierte System-on-Chip - (SoC) - Designs entwickelt wurde () Hochfrequenz 8211 bis 200 MHz 0,13u am schlechtesten Fall-Prozess Leistungsaufnahme: Aktiver Modus - mit voller DSP-Fähigkeit Langsam-Modus - Taktrate und Stromverbrauch, linear geteilt, relativ zum aktiven Modus durch einen benutzerdefinierten Faktor und Stopp-Modus - Leckstrom nur Hohe Code-Dichte mit 16-Bit-Befehlsbreite CEVA-X1620 DSPCEVA-X1620 ist die erste Implementierung der CEVA-X DSP-Familie, bestehend aus 16-Bit-Datenbreite und zwei MAC-Einheiten () CEVA-X1620 Zielmärkte umfassen 3G-Mobiltelefone und Software-Radio, Smartphones PDAs, Video und Audio-Verarbeitung für mobile Geräte, VoIP-Gateways und Breitband-Modems und Home Entertainment (Digital TV, HDTV, PVR, HD-DVD) Dual MAC 16-Bit Fixpunkt DSP Kombination von VLIW - und SIMD-Architekturkonzepten Im Rahmen der CEVA-Toolbox Software-Entwicklungsumgebung () Projekt-Build-Optimierer: Erstellt optimierte Build-Konfigurationen, simuliert und profiliert mehrere Anwendungsszenarien auf Basis der Kundenanwendung und genaue Systembedingungen DSP - und Kommunikationsbibliotheken: C-aufrufbare Montage optimierte Funktionen, verbessern die Performance - und Entwicklungszeit von DSP und Kommunikationsanwendungen Anwendungsprofiler: Ein zyklusspezifischer C-Level-Applikations - und Speicher-Subsystem-Profiler Ein leistungsstarker, leistungsstarker Dual Multiply-Accumulate (MAC), 16-Bit-Fixpunkt-DSP-Kern () Integrierte, programmierbare Audio-Plattform: DSP-Kern und Subsystem Breites Spektrum an Audio-Codecs Kurze Zeit zum Markt Niedriges Risiko () Robuste Leistung: Niedrige Kosten - 0,5 mm2 für den DSP bei 65nm Prozess Niedrige Leistung - 0,5 mW für Stereo-MP3-Decoder Starkes Technologie-Erbe: Nutzen Sie weit verbreitete CEVA - TeakLite-Technologie Audio-Codecs, die in Schlüsselzellen - und Consumer-Geräte-Märkten eingesetzt werden Single-Source-Lösung: Reduziert Risiken und Lösungskomplexität Die AMC-D24AF4-RF2 ist eine hochintegrierte AdvancedMC (AMC) - Karte mit zwei Breitband-HF-Transceiver-Kanälen. Der Modul22683648482s Hauptprozessor ist der KeyStone2268222162 II Architektur-basierte TCI6638 Digitale Signalprozessor (DSP) ARM194174 SoC, der acht TMS320C66x DSP Kerne enthält, sowie vier ARM Cortex194174-A15 Kerne für höhere Schicht Verarbeitung. Das Modul hat auch zwei C6678 DSPs, plus ein großes Xilinx Kintex-7 FPGA. () AMC-D1F1-1200Unsere AdvancedMC-Modul, das eine kompakte, leistungsstarke DSPFPGA-Signalverarbeitungslösung für AdvancedTCA - und MicroTCA-Systeme anbietet () Texas Instruments TMS320C6455 digitaler Signalprozessor mit 1,2 GHz und einem Virtex-4 FX100 FPGA von Xilinx Optimiert für Anwendungen Erfordert eine High-End-Signal-IO-Bandbreite in einem kompakten Mid-Size-AMC-Formfaktor wie drahtloses Basisband, Bildverarbeitung, Verteidigung und Luft - und Raumfahrt Bietet eine Kombination aus DSP - und FPGA-Ressourcen mit schnellen und flexiblen Verbindungen zu externen Daten und über 256 MB Von Onboard-Speicher Eine hochintegrierte AdvancedMC-Karte basierend auf TI22683648482s TCI6636 und TMS320C6678 DSP SoCs sowie eine große Xilinx Kintex-7 FPGA und 4x4 RF. Der AMC-D24A4-RF4 ist eine hochleistungsfähige ARM-, DSP - und FPGA-basierte Verarbeitungskarte mit vier integrierten, flexiblen Breitband-HF-Transceiverkanälen. Das Modul richtet sich an LTE-, LTE Advanced - und 5G-Systeme, die MIMO-Technologien erfordern und die komplette RF-Layer-3-Wireless-Base-Funktionalität auf einer einzigen AdvancedMC-Karte implementieren können. Der Modul22683648482s Hauptprozessor ist der TCI6636 KeyStone II DSPARM SoC. Es umfasst acht C66x DSP Kerne, sowie vier ARM Cortex2268222162-A15 Kerne für höhere Schicht Verarbeitung. Das Modul hat auch zwei TMS320C6678 oktale C66x Kern DSPs. Alle Prozessoren sind eng über TI22683648482s Hyperlink-Schnittstelle und die Ethernet-Infrastruktur der Karte mit Serial RapidIO (SRIO) Backplane-Konnektivität, die Inter-Card-Konnektivität. Es gibt auch eine große Kintex-7 FPGA für zusätzliche Co-Verarbeitung und die Verwaltung der RF-Schnittstelle EIGENSCHAFTEN: 1 Texas Instruments TCI6636 SoC DSP 2 Texas Instruments TMS320C6678 SoC DSPs Jeder DSP hat 8 Kerne - 24 DSP Kerne insgesamt 4 HF-Kanäle, jeweils Unterstützt FDD oder TDD 662MHz - 3.84GHz 20Gbps Gen2 RapidIO zu AMC.4 konforme Backplane 3x SFP zu FPGA, bis zu 10,3 Gbaud Gigabit Ethernet Schnittstelle Integrierter GPS Empfänger Doppelte Breite, Full-Size AMC Karte. () Die AMC-2C6678L ist eine Hochleistungs-DSP-Karte. Es wird von den neuesten Texas Instruments SoC TMS320C6678 DSPs angetrieben. Die 16 C66x DSP Kerne sind mit Hochgeschwindigkeits-Hyperlink-, PCIe - und SRIO-Verbindungen verbunden und eignen sich hervorragend für eine Reihe von Hochleistungs-DSP-Verarbeitungsanwendungen wie Bildsensorbearbeitung, Telecomms und Stepper-Steuerung. Darüber hinaus kann es für DSP-basierte Beschleunigung von Sprach-und Video-Anwendungen verwendet werden. Die Kerne arbeiten bei 1,25 GHz und haben die kombinierte Leistung, um 320 GFLOPS und 640 GMACS zu verarbeiten. Die Platine wird mit Software-Support-Bibliotheken geliefert und 3L Diamond wird auf dieser Plattform für fortgeschrittene Multiprozessor-Code-Entwicklung voll unterstützt. CommAgility kann Ihre Bedürfnisse unterstützen, wenn Änderungen erforderlich sind, um dieses Produkt an Ihre OEM-Anforderungen anzupassen. EIGENSCHAFTEN: 2 Texas Instruments TMS320C6678 DSPs Jeder DSP hat 8 C66x Kerne, die bei 1,25 GHz arbeiten (16 DSP Kerne insgesamt) PCI Express Gen 3 Link zu AMC.1 konforme Backplane mit On-Board-Switch 20 GBB Gen2 RapidIO zu AMC.4 konforme Backplane. Vollständige Gigabit-Ethernet-Infrastruktur Einzelbreite, mittelgroße AMC-Karte (Full-Size-Option erhältlich). . (DSC) von Texas Instruments Incorporated (TI) () Die beiden Module nutzten die branchenführende Leistung von TIs. (2), die auf der Basis der neuesten leistungsstarken TMS320TCI6616 Basisstation System-on-Chip (SoC) und TMS320C6670 Digitalsignalprozessor (DSP) Neue Geräte und fügen Sie High-Speed, flexible IO, um Lösungen für drahtlose Basisstation und leistungsstarke Anwendungen zu liefern Die Module beinhalten auch ein Xilinx LX240T Virtex-6TM FPGA für zusätzliche IO und Co-Processing Flexibilität Der AMC-2C6616 enthält TIs neue CI6616 SoC Basisstation und zielt auf LTE-Wireless-Basisstation-Anwendungen, einschließlich Entwicklung, Versuche und endgültige Bereitstellung auf dem Gebiet Die AMC-4C6678 ist eine Hochleistungs-DSP-Karte. Es wird von den neuesten Texas Instruments SoC TMS320C6678 DSPs angetrieben. Die 32 C66x DSP Kerne sind mit Hochgeschwindigkeits-Hyperlink-, PCIe - und SRIO-Verbindungen verbunden und eignen sich hervorragend für eine Reihe von Hochleistungs-DSP-Verarbeitungsanwendungen wie Bildsensorbearbeitung, Telecomms und Stepper-Steuerung. Die Kerne arbeiten bei 1,25 GHz und haben die kombinierte Leistung, um 640 GFLOPS und 1280 GMACS zu verarbeiten. Die Platine wird mit Software-Support-Bibliotheken geliefert und 3L Diamond wird auf dieser Plattform für fortgeschrittene Multiprozessor-Code-Entwicklung voll unterstützt. EIGENSCHAFTEN: 4 Texas Instruments TMS320C6678 DSPs Jeder DSP hat 8 C66x Kerne, die bei 1,25 GHz arbeiten (32 DSP Kerne insgesamt) PCI Express Gen 3 Link zu AMC.1 konforme Backplane mit On-Board-Switch 20 GBB Gen2 RapidIO zu AMC.4 konforme Backplane. Vollständige Gigabit-Ethernet-Infrastruktur Einzelbreite, Full-Size-AMC-Karte. (AMC-K2L-RF2Die AMC-K2L-RF2 ist eine kostengünstige, leistungsstarke ARM - und DSP-basierte Verarbeitungskarte auf Basis von TIs TCI6630K2L SoC, die zwei integrierte Breitband-HF-Transceiver-Kanäle umfasst, die alle in der kompakten Advanced Mezzanine Card (AMC) Formfaktor. Es ist entworfen, um die drahtlose Basisbandverarbeitung und eine 2x2 MIMO-Luftschnittstelle in Funktestsystemen, kleinen Zellen und UEs für Standard - oder spezialisierte LTE - und LTE-Advanced-Systeme bis hin zu Release 10 zu unterstützen. () VPX-D16A4-PCIEThe VPX - D16A4-PCIE ist eine robuste Hochleistungs-DSP - und FPGA-basierte Karte im kompakten VITA 65, 3U OpenVPX Formfaktor mit einer schnellen Gen2 PCI Express (PCIe) - Schnittstelle. () AMC-2C6678Die AMC-2C6678 ist eine Hochleistungs-Signalverarbeitung AMC-Karte mit 16 DSP-Kerne und FPGA-Ressourcen. Es wird von den neuesten Texas Instruments TMS320C6678 DSPs plus ein Xilinx Virtex-6 FPGA angetrieben. Es ist ideal für eine Reihe von Hochleistungs-DSPFPGA-Verarbeitungsanwendungen wie Telekommunikation und Bildverarbeitung. Ein IDT CPS-1848 Gen2 SRIO Switch bietet eine 20Gbps pro Port Serial RapidIO Infrastruktur. Jetzt mit 1.2GHz DSPs mit jeweils 1GB SDRAM. (). CA-AMC-D4F1A Einbrechiges AdvancedMC-Modul für hochbandige, leistungsstarke Signalverarbeitung für DSP - und FPGA-Verarbeitung und 10 Gbit / s Serial RapidIO () Eine DSP-Platine für mathematische Multichannel-Telefonieanwendungen wie Internet-Sprach - und Fax-Gateways () Liefert bis zu 7200 MIPS der digitalen Signalverarbeitungsleistung, genug zu verarbeiten (dh Sprach - und Fax über IP) bis zu sechs T1- oder E1-Leitungen in Echtzeit Mit einer Vielzahl von Standard-WAN - und Telefonie-Mezzaninen, einschließlich T1, E1, SCSA und ATM können mit bis zu 72 100 MHz TMS320VC549 DSPs ausgerüstet werden, die als sechs Mini-PCI-Mezzanine implementiert werden. High-Density DSP Telecom CompactPCI Board () Robuster, leistungsstarker OpenVPX DSP (Digital Signal Processing) Motor Basierend auf Intel Next-Generation Quad-Core-Prozessor-Technologie () VPX3-453 3U VPX Virtex-68640D DSPDie VPX3-453 ist eine leistungsstarke, kleine Formfaktor DSP-Engine, die ein Xilinx194174 Virtex174-6 FPGA und ein Freescale174 Power Architecture MPC8640D Prozessor kombiniert . Diese kleine Formfaktor 3U VPX (VITA 4648) Karte ist ideal für SWaP-beschränkte Umgebungen und wurde entwickelt, um den vollen -40 85 Grad C robusten Betriebstemperaturbereich zu unterstützen. Die VPX3-453 beschleunigt und vereinfacht die Integration von fortschrittlichen DSP - und Bildverarbeitung in eingebettete Systeme, die für anspruchsvolle Radar Processing, Signal Intelligence, ISR, Image Processing und Electronic Warfare Anwendungen entwickelt wurden. () DSP-basierte Datenerfassungs-Subsysteme Eine Reihe von Multiprozessor-DSP-Karten und - Modulen, die in komplette Datenerfassungs-Subsysteme integriert sind () Entworfen für industrielle Prozess - und Steuerungsanwendungen Lieferung von 6400 MIPS-Fixpunkt-DSP-Leistung bis zu 16 GFLOPS-Gleitkomma-Leistung in einem einzigen 6U VMEbus - oder CompactPCI-Steckplatz Basierend auf Ixthos CHAMP-Architektur ProWare PMC-440A robuste FPGA-PMC-Karte für die Erfassung, Verarbeitung und Ausgabe von Daten, die von Hochgeschwindigkeitssensoren wie elektrooptischen Infrarot - (EOIR-) und Radarsystemen abgeleitet werden () Onboard FPGA liefert Bis zu 20 Milliarden Operationen für FFT - und Digitalfilter DSP-Funktionen Kann mit einer der beiden Versionen des Xilinx Virtex-II Pro FPGA konfiguriert werden: der XC2VP20 (9.280 Logic Slices88 18x18 Multiplikatoren) oder der XC2VP40 (19.392 Logic Slices192 18x18 Multiplikatoren) 64 - bit, 66 MHz PCI-Schnittstelle mit Unterstützung für PCI-X CHAMP-AV5 6U VMECurtiss-Wright steuert den ersten DSP-Motor mit dem neuen Intel Core i7-Prozessor () bringt die Gleitkomma-Performance der Intel Core i7-Architektur auf den VME64x-Formfaktor-Standard Ein Paar von 2,53 GHz Dual-Core Core i7 Prozessoren, bietet der CHAMP-AV5 bis zu 81 GFLOPS der Performance High-Bandbreite PCIe-Architektur, mit Onboard-PCIe-Verbindungen zwischen den Prozessoren und den PMCXMC-Standorten CHAMP-XD2M 6U OpenVPX Intel Xeon D DSPDie 6U OpenVPX CHAMP-XD2M robustes Intel Xeon D Modul ist für den Einsatz in hohen Speicherkapazitäten, rechenintensiven Anwendungen für Industrie, Luft - und Raumfahrt und Verteidigung konzipiert und ermöglicht es Entwicklern von High Performance Embedded Computing (HPEC) - Systemen, die unübertroffene Leistung von heute22683648482s zu nutzen - edge Xeon Prozessor D Architektur. () CHAMP-AV IVDie dritte Generation unserer Quad-PowerPC-DSP-Karten mit der QuadFlow-Architektur, die Verbindungen zwischen vier 7447A7448-Prozessoren () Quad PowerPC 7447A7448 Prozessoren mit bis zu 1,25 GHz bis zu 512 MB DDR-250 SDRAM mit ECC pro Prozessor ( 2 GB gesamt) und 64 KByte L1 und 1 MByte (7448) L2 interne Caches, die mit Kernprozessor-Geschwindigkeit arbeiten QuadFlow-Architektur mit 3,2 GB Peak On-Board-Durchsatz PCI V2.2-kompatible 64-Bit-Universal-PCI-Karte () Eine hohe Leistung DSP-Platine optimiert für hochverfügbare, hochverstärkte digitale Signalverarbeitungsanwendungen () Eine hochleistungsfähige DSP-Platine, optimiert für hochverfügbare, hochverstärkte digitale Signalverarbeitungsanwendungen () Eine TMS320C6200 DSP-Design-Suite, die TIs eXpressDSP Echtzeit-Software unterstützt Technologie () Bit-true Fest - und Fließkomma DSP-Systemdesign C-Code-Generierung Integriert mit Code Composer Studio für Rapid Prototyping Eine neue Version von SystemView, die die Designzeit für DSP - und Wireless-Kommunikationssysteme reduziert, indem sie zusätzliche Modellierungs-, Analyse - und Debugging-Funktionen ( ) Design und Simulation sorgen dafür, dass das RF-Frontend, der AD-Wandler und die DSP-Funktionen alle korrekt zusammenwirken. Enthält Erweiterungen der SystemViews-Analyse und Debugging-Fähigkeiten Ein Designer kann ein Signal über ein ganzes System verfolgen, indem er einfach eine virtuelle Sonde bewegt Die Ausgabe jedes Blocks des Blockdiagramms während der Systemsimulation Ein System-Level-Design-Tool für DSP - und Kommunikationsanwendungen () Bietet Simulink-Integration, verbesserte Filter-Design-Tools und ein bedeutendes neues Angebot an Modellen für Kommunikationsanwendungen Eine erweiterte Kommunikationsbibliothek umfasst TDMA-Multiplexer-Demultiplexer , OFDM Modulationsdemodulation, Gold Code Generator, Punktion, Deponanz und QAM Detektor, Mapper, Demapper Modelle Die RFAnalog und DSP Bibliotheken enthalten auch neue Modelle Ein universelles DSP Entwicklungssystem, das den Aufbau von skalierbaren DSP Systemen ermöglicht () System kommt in einem 19 Zoll , 3U robustes Gehäuse mit einem einzigen Atlas-Board Das Atlas I-Board verfügt über zwei 120 MFLOPS-Gleitkomma-ADSP-21060-Prozessoren Das Atlas II-Board verfügt über zwei 480 MFLOPS ADSP-21160-Prozessoren Virtuose 4.1 Eine integrierte Entwicklungsumgebung für Echtzeit-Embedded-Systeme, Ein vierschichtiges, mikrokernelbasiertes RTOS, das für DSP - und ASIC-Cores optimiert ist () Benötigt 2 Kwords auf 10 Speicherplätze und unterstützt DSPs und RISC-Cores aus Analog Devices, ARM, Infineon und Texas Instruments Tool Suite beinhaltet ein Projekt Manager, ein kerneloptimierendes Systemgenerierungswerkzeug und grafische Analyse - und Debugging-Tools für DSPs Scheduling-Optionen beinhalten Round-Robin mit Priorisierung, Time-Slicing und priorisierte, präventive Scheduling Ein universeller digitaler Signalcomputer () CompactPCI Formfaktor, der von einem Pentium läuft Windows NT Target System besteht aus einem oder mehreren DSP Boards mit je 2 ADSP-21060 (SHARC) Ein TMS320C620x Fixpunktbasierter Universal Digitalsignalrechner () Das MSC8156 Evaluation Module (MSC8156EVM) ist ein kostengünstiges Werkzeug für Ingenieure, MSC815x und MSC825x Familie von Freescale Digital Signal Processors (DSPs) () Die DSCs MSC815x und MSC825x sind hochintegrierte DSP Prozessoren, die ein, zwei, vier oder sechs StarCore SC3850 Kerne enthalten. Die Familie unterstützt roh programmierbare DSP Leistungswerte von 8 GMACs Bis zu 48 GMACs, wobei jeder DSP-Kern mit 1 GHz betrieben wird. Diese Geräte richten sich auf hochauflösende, hochrechnerische DSP-Anwendungen wie 3GPP, TD-SCDMA, 3G-LTE und WiMAX Basisstationsanwendungen sowie Luft - und Raumfahrt und Verteidigung, medizinische Bildgebung, Video , Sprach - und Test - und Messanwendungen MSC8256Das MSC8256 basiert auf dem branchenführenden DSP-Kern, der auf der StarCore-Technologie basiert und für die fortschrittlichen Verarbeitungsanforderungen und - fähigkeiten der heutigen leistungsstarken High-End-Industrieanwendungen für die medizinische Bildgebung, die Luft - und Raumfahrt entwickelt wurde , Verteidigung und fortschrittliche Test - und Messmärkte () Es liefert branchenführende Leistung und Energieeinsparungen und nutzt 45-nm-Prozesstechnologie in einem hochintegrierten SoC, um eine Leistung zu liefern, die einem 6-GHz-Single-Core-Gerät entspricht. Die MSC8256 hilft den Geräteherstellern, Endprodukte und Services zu schaffen, die mehr Funktionalität in einem kleineren Hardware-Fußabdruck integrieren. Der MSC8256 DSP bietet ein hohes Maß an Leistung und Integration und kombiniert sechs neue und erweiterte, vollständig programmierbare SC3850-Kerne mit jeweils bis zu 1 GHz . Der SC3850 DSP-Kern wurde unabhängig beurteilt, um 40 Prozent mehr Verarbeitungsmöglichkeiten pro MHz zu ermöglichen als der nächste DSP-Wettbewerb. Ein leistungsstarkes internes RISC-basiertes QUICC Engine-Subsystem unterstützt mehrere Netzwerkprotokolle, um einen zuverlässigen Datentransport über Paketnetzwerke zu gewährleisten, Die DSC-Kerne MSC8156Die MSC8156 basiert auf dem branchenführenden DSP-Kern, der auf der StarCore-Technologie basiert, mit einer zusätzlichen Leistung von einer Multi-Accelerator Platform Engine (MAPLE-B) für Fast Fourier Transforms (FFT), Inverse Fast Fourier Transforms (iFFT) , Diskrete Fourier-Transformationen (DFT), Inverse diskrete Fourier-Transformationen (iDFT) und Turbo - und Viterbi-Decodierung () Der MSC8156 unterstützt die fortschrittlichen Verarbeitungsanforderungen und - fähigkeiten der heutigen leistungsstarken medizinischen, Luft - und Raumfahrt - und Verteidigungs - und fortschrittlichen Test - und Messmärkte - Leading-Performance und Energieeinsparungen, die 45-nm-Prozesstechnologie in einem hochintegrierten SoC nutzen, um eine Leistung zu erzielen, die einem 6-GHz-Single-Core-Gerät entspricht. Das MSC8156 hilft Geräteherstellern, Endprodukte und Services zu schaffen, die mehr Funktionalität in einem kleineren Hardware-Footprint integrieren Ein Gerät, das es dem Host-Debug-System ermöglicht, mit dem Motorola DSP-Zielsystem über den JTAGOnCE-Connector zu kommunizieren () Befehle, die vom Host eingegeben wurden, werden analysiert und eine Reihe von Befehlssatzpaketen mit niedrigem Pegel werden an den Befehlsumrichter gesendet, Übersetzt Schlüsselpakete mit niedrigem Pegel in serielle Sequenzen, die über den OnCE-Port an den Ziel-DSP übertragen werden. Das Command Converter Kit enthält einen Command Converter, eine Softwareentwicklungswerkzeug-CD und eine Command Converter-Produktdokumentation Command Converters sind Ethernet, PCI, Parallel und Universal (ISASBUS). . Core SC140-basierter DSP mit einem 300 MHz DSP-Kern Vier ALUs bieten 1200 DSP MIPS, 150 MHz programmierbare Netzwerkprotokoll-Engine, 512 KByte Onchip SRAM, 100 MHz 64-Bit - oder 32-Bit PowerPC Bus-Schnittstelle und einen programmierbaren Speicher Controller On - chip 300 MHz verbesserter Filterkompressor und zentraler DMA-Engine Hochwertige Applikations-Enabling-Software-Option für schnelle Time-to-Market () Framework-Level-Software-Option fügt Flexibilität hinzu, um Algorithmen und Verbindungen hinzuzufügen Board - und Bibliotheksniveau-Software-Option für ultimative Kontrolle Neueste Generation DSPs für Niedrige Kosten und Leistungsaufnahme pro Kanal DSP56F801A DSP-Kern basierend auf einer Harvard-Architektur, bestehend aus drei parallel geschalteten Ausführungseinheiten, die bis zu sechs Operationen pro Befehlszyklus erlauben () Mikroprozessor-Programmiermodell und optimierter Befehlssatz ermöglichen die Generierung von effizienten , Kompakter Code für DSP - und MCU-Anwendungen Bedienungsanleitung ist für C Compiler sehr effizient, um eine schnelle Entwicklung von optimierten Steuerungsanwendungen zu ermöglichen Integriertes Programm Flash und Daten Flash-Speicher Ein 24-Bit-Mehrkanal-Audio-Decoder DSP optimiert für kostenempfindliche Verbraucher Audio-Anwendungen () Unterstützt alle gängigen Multichannel-Audio-Decodierungsformate, darunter Dolby Digital Surround, Moving Picture Experts Group Standard 2 (MPEG2) und Digital Theatre Systems (DTS), in einem einzigen Gerät mit ausreichend MIPS-Ressourcen für kundenspezifische Post - Verarbeitungsfunktionen wie Bassmanagement, 3D virtueller Surround, Lucasfilm THX5.1, Soundfield-Verarbeitung und erweiterte Entzerrung Verwendet den Single-Instruktion-per-Clock-DSP56300-Core unter Beibehaltung der Code-Kompatibilität mit der DSP56000-Kernfamilie Enthält audio-spezifische Peripheriegeräte Und ein Onboard-Software-Surround-Decoder und wird in 100 MHzMIPS und 120 MHzMIPS Versionen bei 3.3V angeboten. Ein DSP-Kern auf Basis einer Harvard-Architektur, bestehend aus drei parallel arbeitenden Ausführungseinheiten, die bis zu sechs Operationen pro Befehlszyklus erlauben () Mikroprozessor-Programmiermodell und optimierter Befehlssatz ermöglichen die Erstellung eines effizienten, kompakten Codes für beide DSP - style and MCU-style applications Instruction set is highly efficient for C Compilers to enable rapid development of optimized control applications Integrated program Flash and data Flash memories A StarCore-based DSP with four 300 MHz Star () Core SC140 DSP extended cores 16 ALUs onchip deliver 4,800 MMACS, 12 G RISC MIPS (Performance equivalent to a 1.2 GHz SC140 core) Four 300 MHz EFCOPs P2020-MSC8156 AdvancedMCThe Freescale P2020-MSC8156 AdvancedMC (AMC) reference design is a multi-standard baseband development platform for the next generation of wireless standards such as LTE, WiMAX, WCDMA and TD-SCDMA. () A single-chip RISC microprocessor () 32-bit RISC-type SuperH RISC engine architecture CPU with digital signal processing (DSP) extension Cache memory, on-chip XY memory, and memory management unit (MMU), as well as peripheral functions required for system configuration Includes data protection, virtual memory, and other functions provided by incorporating an MMU into a SuperH Series microprocessor (SH-1 or SH-2) USB-connected Software-Defined Digital Radio system () Ready-to-Go SystemA ready-for-use low-cost system including USB-connected programmable FPGA and DSP hardware () Includes USB-connected FPGADSP hardware of the users choice, USB cable, IO cables to interface to peripherals, main power supply unit, and CD containing software tools, examples, and documentation Connects to PCs using high-speed USB Allows users to download FPGA designs, then exchange data between the FPGA and PC at speeds up to 40 Mbps HERON DSP SystemsHERON high-performance modular signal processing systems for PCI-based, USB connected, and Embedded use are programmable and reconfigurable, using common APIs to provide compatibility and complete flexibility () Choose one or combine any number of our off-the-shelf modules Modules with Xilinx Virtex FPGA (with external memory options plus digital and analog IO choices) and TI 8216C6000 DSP Mount selected modules on a HERON module carrier which provides real-time data connections with 400 Mbps possible in each direction simultaneously HERON-IO2A FPGA module with Virtex II 1M gates plus two channels of 12-bit 125 MHz AD and two channels of 14-bit 125 MHz DA () Analog serial bandwidth of 500 MHz in and 145 MHz out When fitted to a HERON module carrier, can have its FPGA 8220program8221 downloaded from the PC over the HERON serial bus, allowing users to program and reprogram the FPGA IP available for commonly used functions HERON-FPGA12HERON module with Virtex-4FX12 FPGA plus DDR SDRAM, flash memory, and 60 bits digital IO () HERON-FPGA3A FPGA module with digital IO () PlugPlay PCI 2.1 33MHz32-bit slave, MasterSlave (optional) support Up to 400k gates in Spartan-3 family FPGAs Spartan-3 FPGAs system clock rate up to 320 MHz A configurable and scalable RTOS architecture for convergent processing () Uses two real-time kernels: RTXCss, and single-stack, thread-based kernel, and RTXCms, a multi-stack task-based kernel Meets the requirements of real-time, control-processing, or Digital Signal Processing (DSP) applications Supported processors: ARM 77T, 99T, Motorola DSP56F800, Motorola DSP65300600, Motorola ColdFire family, Motorola PowerPC, Motorola StarCore MSC8101, and Texas Instruments TMS320C54x, TMS320C55x . A real-time multi-tasking kernel (RTXC) for Motorolas DSP 56303307309EVM digital signal processors () Motorolas Suite56 Software Development Tools include a processor simulator, C compiler, assembler and linker, and a hardware debugger This suite of tools and RTXC form a new embedded development environment Features include: (1) small code footprint of about 1,500 to 4,500 words (2) full source code and no run-time royalties (3) support of nested interrupts (4) extensive interrupt handling models and examples (5) macros to simplify the creation of interrupt service routines (6) support for mixed assembly language and C programming and (7) a GUI-driven system generation utility that allows specification and generation of RTXC system objects without having to know the internals of the kernel objects A software development kit based on Texas Instruments TMS320DSC2 DSP () Provides developers access to the complete DSPLinux simulation and hardware environment through DevelopOnline DSPLinux is optimized for multimedia applications in which DSPs offer high processing power with low battery consumption Focused on dual-core ARMDSP architectures, with the Linux kernel residing on the ARM processor to control the operation of the DSP From Microchips PIC24 16-bit MCUs through the dsPIC 30 to the dsPIC 33, DSPnano has seamless support including CC integrated development environment (IDE), a DSP RTOS, and DSP libraries () CC IDE based on Eclipse with a highly productive user interface DSPnano operating system level simulator Seamless integration with Microchips MPLAB IDE for instruction-level simulation, compiling, and debugging using ICD2 or REAL ICE A signal processing operating system intended for small signal processors and small DSP networks () Enables adding real-time signal processing capabilities () PCI Mezzanine Card (PMC) is a widely used industry standard for small-sized mezzanine modules A high-performance DSP processor and graphical application development in LabVIEW Suitable for real-time processing applications SI-C6713DSP-PC104pAn embedded PC104-Plus DSP board () Texas Instruments TMS320C6713 DSP at 300 MHz Up to 256 MB of SDRAM using conventional 144-pin SODIMMs 2.25 W typical power consumption PCI, CompactPCI, PMC, PC104-Plus form factors () SI-C6713DSP-PCIDSP board for data acqusition, measurement, and digital control applications () SI-C33DSP-cPCIReal time software accelerator board for LabVIEW based on Texas Instruments TMS320VC33 family of floating point DSPs () SI-C6713DSP-(PCI)Real time software accelerator board for LabVIEW and Visual Basic based on TIs TMS320C6x family of floating point DSPs () DSP board for PC104-Plus () 1,800 MFLOP peak performance with C6713, 1,200 MFLOPs with C6711, 32 bit floatingfixed point precision Up to 256 MB SDRAM, using conventional PC133 SDRAM SODIMM format Full 32 bit bi-directional PCI initiated bus mastering, with 132 MBps peak transfer rate A board providing high-density DSP resources and a high level of general purpose, programmable MIPS per square mm () Compliant with 64xx IP video, transcoding, wireless, and voice algorithms Includes WinXP and Linux drivers and C code API, full DSP software, DSP with real-time examples Up to eight C6414, C6415, or C6416 DSPs A DSP board that combines a 32-bit floating-point TMS320C44 DSP with up to 512K x 32 SRAM and high-speed, multiple IO paths for connectivity to analog IO or other peripheral PC104 boards or other C4x processors () Four comm - port connectors, 32-bit 8220GlobalBus8221, and EPROM or Flash EEPROM site Supported by DSPower and Hypersignal software . SigC5502Dual DSP 24-bit audio board () Dual 300 MHz C5502 processor sites Stereo 24-bit 96 kHz audio IO, 100 dB SNR typical Single-ended and differential-ended audio connector options SigC67xx-SODIMMA quad processor DSP module () Up to four Texas Instruments C67xx processors Up to 5.4 GFLOPS 32-bit floating-point performance 4M x 32 off chip SDRAM and 64k x 32 zero-wait-state onchip SRAM per processor 300 to 480 MIPS Multiprocessor DSP Modules () 384768k x 16 SRAM Three 100 to 160 MHz C549, C5402, C5409, or C5416 cores, in three 144-pin GGU packages, each with separate 2.5v (or 1.8v) core and 3.3v peripheral voltages 128k x 16 or 256k x 16 zero-wait-state external SRAM per core A PTMC card that condenses the Texas InstrumentsTelogy Phase III High-Density VoIP reference design 8211 including DSP farm and network processor 8211 into PMC form factor () IP telephony applications include echo can farm, transcoding server, media gateway, complete soft switch solution using onboard host processor, Asterisk PBX, and more Telogy software compliant OC-3 channel capacity A modular DSP resource board () Provides up to 1920 MIPS in a single PC104 form factor Accepts off-the-shelf processor modules with Texas Instruments C54xx DSPs and 16-bit audio and speech IO modules, and custom modules, for example H.110 or MVIP subset High-speed host interface Signal Ranger Mk3 is a DSP board featuring a TMS320C6424 DSP running at 590 MHz and a XC3S400 FPGA (Signal Ranger Mk3 Pro. version only) () This DSP board provides 6 analog IOs (96 kHz24-bit) It has been designed for pro-audio and high-performance control applications Communication interfaces include a high-bandwidth USB 2 interface as well as an Ethernet communication interface that allows the remote control of the DSP board over the web (an IP Stack DSP firmware is included) Signal Ranger MK2DSP: TMS320C5502 16-bit fixed point DSP, running at 300 MHz, with 32 Kwords of on-chip RAM () TIGER DSP is a digital signal processing board featuring a Xilinx Virtex 6 FPGA, data memory, and various host connections. () A 6U VMEbus board with a VME64 masterslave interface () Two processors available: single, dual, or quad 1600 MIPS, 200 MHz TMS320C6201B DSPs or single, dual, or quad 1 GFLOPS, 167 MHz MS320C6701 DSPs Up to 2 Mbytes of SBSRAM and 64 Mbytes of SDRAM Hurricane, a single chip PCI bridge optimized for DSP systems CompactPCI DSP system supports TMS320C6701 architecture () Dual or quad processor with distributed shared memory architecture provided by the Hurricane PCI-to-DSP bridge chip SBSRAM distributed shared memory Additional IO capabilities include IP Modules, PMC modules, DSP-Link 3, custom IO, and Spectrum-developed PEM modules which provide 400 Mbytessec of IO bandwidth per DSP Single-channel digital radio receiver module with software demodulation libraries () This surveillance solution combines an AD converter, digital down converter, TMS320C44 DSP processor, and a DA converter on a single-wide TIM-40 module Designed to work with Spectrums LeMans VXI product . InglistonA quad PCI DSP system based on the 250 MHz, fixed-point C6202 processor () A high-performance, programmable digital interface that connects Spectrums 8216C6000-based DSP boards to custom and standard IO systems () Provides up to 100 Mbitssec of IO bandwidth to each 8216C6000 DSP Total data throughput of 200 Mbitssec Programmed to interface to virtually any type of digital IO devices, including digital cameras, motor controllers, and as standard and custom parallel interfaces Single-channel digital radio receiver module with software demodulation libraries () This surveillance solution combines an AD converter, digital down converter, TMS320C44 DSP processor, and a DA converter on a single-wide TIM-40 module Designed to work with Spectrums LeMans VXI product . Multiplatform digital radio receiver consists of MDC44DDC 50 MHz TIM module (1 MByte or 4 MBytes), MD70MAI 70-Msamplesec AD converter TIM module, 50 KHz analog daughter module and DDR cable kit () Scaleable solution maintains interoperability with VXI, ISA, PCI and VME platforms Incoming signals from an antenna system digitized by TIM-40 based AD converter and forward via 1.4 Gbits G-Link network to one or more TIM-40 based receiverDSP blocks for demodulation and analysis Easily daisy-chained . An octal VMEbus processing engine () Eight 250300 MHz 8216C6203 fixed-point processors Peak performance of 16,00019,200 MIPS Solano-based architectures provides 200 Mbytessec full-duplex links between processors PRO-4600A 3U CompactPCI processing engine that uses a combination of FPGA, DSP, and GPP to support black-side signal processing for software defined radio (SDR) applications () 3U CompactPCI form factor Available in conduction-cooled and air-cooled versions Rugged conduction-cooled carrier versions follow the IEEE 1101.2 specification and operate with ANSI VITA 20 compliant XMC modules Barcelona-HSA 6U, hot-swap CompactPCI board combining DSP multiprocessor hardware and software tools for designing high availability systems () A DSP-based digital radio PMC mezzanine for use with Spectrums TMS320C6x-based carrier products () The PMC-MAI is a 65 M samplessec analog input PMC, the PEM-2PDC is a dual-programmable down converter module, and the PEM-4PDC is a quad-programmable down converter module Both PEM modules are based on Spectrums Processor Expansion Module (PEM) open specification For commercial and military signals intelligence or surveillance applications ePMC-8310A Texas Instruments TMS320C6416C6415 DSP-based multiprocessing engine for communications applications () Choice of one or two 600 MHz TMS320C6416 or TMS320C6415 fixed-point DSP processors with a peak performance of 4800 MIPS per processor Integrated Viterbi and Turbo co-processors Eight dedicated high-speed data paths to the DSPs, connected through a programmable router for dataflow reconfigurability AcceleraA graphically-driven, modular, system-level software tool, designed to speed the development of multiprocessor DSP applications for Spectrums multi-DSP TMS320C620203 products () A PCIe-based carrier card with dual XMC sites () Can be used within a PC-based system to interface to Spectrum FPGA, DSP, and IO processing engines Flexible data routing architecture, allowing numerous combinations of FPGA, DSP and GPP signal processing devices Supports applications requiring high-speed, low latency, deterministic data paths The LeMans 840 MFLOP octal TMS320C4x VXIbus master board can host up to six single-wide or four double-wide C4044 DSP modules and TIM-40 form factor SRAM, DRAM, EDRAM, or IO modules () Supports VXI shared memory, VXI masterslave modes, and 80 Mbytessec data transfers via the HP local bus Features JTAG input and output connectors, a test bus controller, and device driver support via VISA or SICL . An expansion module that connects high-speed digital signal processors (DSPs) to the Internet () Allows a sophisticated collection of DSPs to connect to EthernetInternet directly and without involvement of a host computer Uses Texas Instruments 225-MHz TMS320C6713 DSP, based on TIs high-performance, advanced VelociTI VLIW architecture NetSilicon Net-50 ARM CPU ICE105: Embedded IO Programmable SystemSUNDANCE is a worldwide supplier and manufacturer of industrial-class PCIe104 digital signal processing (DSP), configurable small form factors and COTS embedded systems. The ICE105 is a rugged system built around a complete range of PCIe104 small form factor, stackable IO-configurable and programmable solutions. () A library of floating-point DSP vectors and functions () Broad range of callable functions significantly reduces the development time of many DSP applications targeting Texas Instruments (TI) TMS320 DSP-based platforms Hand-coded and optimized functions Includes a data conversion unit that facilitates the conversion of fixed-point and integer formats into floating-point units, as well as the conversion of floating-point units into integer formats A platform for telecom, image processing, medical, and industrial systems () A CompactPCI, multi-DSP system () Four C6416, 600-MHz DSPs, with 32 MB of private SDRAM memory for each DSP Up to 800 MBps IO bandwidth per DSP Optional shared memory interface for each DSP A DSP TIM-40 mezzanine that incorporates four 60 MHz TMS320C44 DSPs, and can be used to provide up to 16 DSPs on a VMEbus carrier board () Configured with either 512 Kbytes or 2 Mbytes of SRAM per processor Memory is divided between the processors local and global buses, ensuring optimal performance from the C44s modified Harvard architecture . SMT7005Four C6201 200MHz DSPs 16MB SDRAM 512KB SBSRAM of private memory for each DSP Up to 800Mbytess IO bandwidth per DSP Optional shared memory interface for each DSP () SMT7006Four C6701 167MHz DSPs () 16MB SDRAM 512KB SBSRAM of private memory for each DSP Over 800Mbytess IO bandwidth per DSP using Sundance Digital Bus and Datapipe Links Optional shared memory interface for each DSP Direct connection to C6000 DSP systems () High accuracy signal source through stringent design criteria communications, base stations and Zero-IF subsystems Wireless local loop (WLL) Local Multipoint Distribution Service (LMDS) A TIM mezzanine that hosts one or two TMS320C6x DSPs () Up to 32 Mbytes of onboard memory Enables a truly distributed DSP processing system The modules can be fitted to a VXI carrier board, giving performance from 1 to 8 GFLOPS when using the TMS320C6701 DSP SMT387Integrated DSP, memory, flash, and storage solution () Includes the latest generation Serial ATA controller, a 600 MHz DSP, and Virtex-II Pro Works in an array of modules as a slave or host Can run standalone and use the on-module flash for booting and control of the disk array SMT417Conduction cooled PMCXMC card with 2 TI DSP at 1 GHz each and a Xilinx XC2VP50 FPGA and much memory () Combining a Texas Instruments TMS320DM642 DSP-based digital media processor at 720 MHz and a Xilinx Virtex-4 FX-60 FPGA, the SMT339 packs huge compute power into a small development board () Software support includes TIs Code Composer Studio Integrated Development Environment (IDE) and 3Ls Diamond FPGA Interfaces include serial ports or the Rocket Serial Link Used with a TIM carrier such as the SMT130 for PCI-104 or standalone, designers can be up and running quickly . SMT130Onboard XDS-510 compatible JTAG Master () Global bus bandwidth in excess of 100 MBps Host interface via ComPort in excess of 10 Mbps Can support multi-DSP and FPGA resources A media processing solution offering simultaneous support for Triple Play convergence voice, video, and data (faxmodem), all running on a single DSP () Suitable for equipment manufacturers who develop media gateways, CTI products, and other Media over Packet (MoP) applications Includes the SurfUP Open DSP Framework that enables integration of user-defined algorithms into the DSP, based on simple and intuitive APIs that interface with Surfs DSP software Quick integration for reduced time-to-market SurfUPDSP software components comprised of a media processing solution offering simultaneous support for Triple Play convergence (voice, video, and data (faxmodem)) all running simultaneously on a single DSP () Equipment manufacturers who develop media gateways, CTI products, and other Media-over-Packet (MoP) applications can integrate a specific media type into their DSP software framework and gain from Surfs robust and field-hardened enabling technologies Powered by an easy-to-use and layered API, the SurfUP DSP software components are ANSI-C compliant (with minimal assembler code for optimization) for cross platformcompiler support Field-hardened DSP software components optimized to run specifically on TIs C64xx DSP generation Fully-integrated RoHS-compliant PMCPTMC DSP resource board providing multimedia processing capabilities: voice, video, and data simultaneously () PMCPTMC form-factor DSP farm, pre-integrated with leading CompactPCI and AdvancedTCA chassis Carrierenterprise-grade, field-proven, and cost effective solution saving resources and reducing RD efforts Complete media processing package for audio, video and data (fax and modem) SurfRiderAMC-EVMComprehensive application development environment () Enables telecom applications developers to handle different DSPs Stand-alone desktop unit simulating AdvancedTCA and MicroTCA chassis for resource-efficient telecom development environment Full DSP control and monitoring over GbE connection for reduced application development and testing time SurfRiderAMCA RoHS-compliant AdvancedMC DSP resource board, preintegrated with AdvancedTCA and MicroTCA chassis () Provides flexible yet heavy-duty multimedia processing capabilities Complete media processing package for audio, video, modem, and fax Flexible and scalable modular design supporting up to 8 TI C64x DSPs onboard SurfExpressPCIeFully integrated RoHS compliant PCIe DSP resource board providing multimedia processing capability: voice, video. and data () Graph-based Physical Synthesis fast timing closure and a push-button performance boost of up to 20 percent () RTL-based Verification Technology offers the fastest method of finding functional errors in a design thanks to simulator-like visibility into a live, running FPGA with real-world stimulus Automatic Handling of DSP functions infers DSP functions from RTL and maps into vendors DSP hardware (such as MAC) ASIC design-style support built-in gated clock conversion and a DesignWare compatible library enables ASIC code to be implemented into an FPGA without modification SPW Hardware Design System (HDS)Fastest path from innovation into implementation for digital signal processing systems, applying a model-based design approach () At its core is the C Data Flow (CDF) modeling paradigm, which enables the most efficient description of digital signal processing systems which may be implemented in dedicated digital hardware or embedded software SPW Hardware Design System (HDS) is a key component in the SPW product family It accelerates the hardware design, verification, and analysis of complex, algorithm intensive Digital Signal Processing (DSP) systems Unique Synplify DSP synthesis engine 8211 Automatically creates optimized algorithm RTL architectures from your DSP model () Powerful DSP synthesis optimizations 8211 Exploration of speedareadevice technology trade-offs without changing your DSP model Comprehensive DSP library 8211 With full multi-rate support and advanced fixed-point quantization analysis M-Control feature 8211 Enables use of M-language for concise expression of complex state machine and control logic functionality An application processor for 2.5 and 3G wireless devices () Dual core architecture optimized for efficient operating system and multimedia code execution TMS320C55x DSP provides superior multimedia performance while delivering the lowest system-level power consumption TI-enhanced ARM 925 core with an added LCD frame buffer to run command and control functions and user interface applications StarterWareFree software enables quick and simple programming of TI embedded processors () user-friendly, production-ready software for Sitara2268222162 32-bit ARM194174 microprocessor (MPU), C60002268222162 digital signal processor (DSP) and DSP ARM developers provides application developers with a flexible starting point that does not require the use of an operating system allows for easy migration to other TI embedded devices A client-side telephony DSP system () Provides 14 eXpressDSP-compliant algorithms on one chip, including data, telephony, and voice algorithms For PSTN-connected products Provides an open DSPBIOS real-time kernel software framework with a complete telephony algorithm library, on-chip memory and peripherals A fixed-point, 16-bit DSP dual-core solution () Code Composer (version 3.0) includes a DSP software simulator for Texas Instruments DSPs, including the C6x () Mimics the actual execution of DSP code without the presence of a DSP chip Code Composer is an IDE that allows designers to edit, build, manage projects, debug and profile from a single application Users can: (1) compile in the background (2) analyze signals graphically (3) perform file IO (4) debug multiple processors and (5) customize the IDE via GEL A DSP family targeted toward appliances, industrial products, consumer products, automotive products, and office products () Up to 40 MIPS of processing power from the processing core Onchip Flash or ROM Dedicated peripherals, such as pulse-width modulation, ultra-fast AD converters, and CAN modules Real-time software technology that simplifies and streamlines the DSP product development process, reducing product development time () Comprised of the TMS320 DSP Algorithm Standard, a single, standard set of coding conventions and application programming interfaces (APIs) for algorithm creators to wrap the algorithm for system-ready use Includes the Code Composer Studio integrated development environment (IDE) Includes DSPBIOS, a scalable, real-time kernel and a growing base of TI DSP-based software modules from third parties that can be easily integrated into systems by OEMs Texas Instruments Incorporated is offering developers the industry22683648482s highest performing, scalable and flexible multicore solutions based on its TMS320C66x digital signal processor (DSP) generation. () Fixed - and floating-point capabilities Highly suited for audio infrastructure products as well as vibration and acoustic analyzers Excellent fit for high precision motion control and high channel count real-time process control system An integrated Internet audio chip () Dual Multiply and Accumulate Chip (MAC) on a DSP Embedded Universal Serial Bus (USB) capabilities Supports Secure Digital (SD), Memory Stick, Compact Flash, Smart Media, and Multimedia Card (MMC) TMS320C6472 Multicore DSPSix high speed C64X DSP cores running at 500MHz, 625MHz, 700MHz, and fully backward compatible with other C64X DSP cores () Highest performance DSP from TI with up to 4.2 GHz33600 MMACs and 4.8 MB on-chip L1L2 RAM Offers best power efficiency in the industry with 3GHz performance at 0.15mWMIPS Optimized DSP architecture maximizes subsystem performance on a chip. One of the advantages of this architecture is that in addition to dedicated L1 and L2 memory to each core, the C6472 features 768KB shared L2 programdata memory and a shared memory controller to facilitate high efficient and flexible inter DSP core communications An integrated development environment () Supports C55x and C64x DSPs Includes Visual Code Generation productivity tools, the C6000 Profile Based Compiler, and C5000 Visual Linker Project manager handles thousands of files and supports external make file capabilities to enable working across both PC and Unix Floating-point Digital Signal Processors (DSPs) () Advanced Very Long Instruction Word (VLIW) C67x DSP core L1L2 memory architecture Enhanced Direct Memory Access (EDMA) controller with 16 independent channels A digital still camera chip () TMS320C5000 DSP and ARM7TDMI RISC processor 80 MHz, 32-bit-wide SDRAM interface Programmable CCD controller supports CCDs up to 4M pixels (2K x 2K) Automatically converts ANSI-standard C programs produced by The MathWorks Simulink, DSP Blockset, and Real-Time Workshop algorithm prototyping tools into executable DSP programs () Intuitive block diagram editor models complex systems by selecting the connecting functional elements from the Simulink and DSP Blockset libraries Real-Time Workshop converts Simulink and DSP Blockset block diagram representations into C programs, which are converted into a SPOX program and compiled for the target DSP . A fully programmable DSP-based chip designed specifically for the consumer digital multimedia market () Specifically designed for multimedia applications such as digital video camcorders, PDAs, and other portable imaging and video products Can be used as a stand alone media processor or can seamlessly interface to an external CPU as a slave processor Supports multiple applications and file formats including MPEG4, JPEG, MPEG1, M-JPEG, H.263, mp3, AAC and QuickTime Multi-channel analog interfaces with a user-programmable Spartan-IIE or Virtex-II FPGA, providing developers with the means to implement FPGA-based digital signal processing solutions () Can be used as stand-alone devices with the user-programmable FPGA responsible for supporting all signal processing functionality, or as daughtercards to micro-line DSPFPGA boards A variety of multi-channel ADA configurations are supported: 2-channel 14-bit ADA with ADC sample rates up to 65 MSps 4-channel 16-bit ADA with ADC sample rates up to 2.5 MSps 12-channel ADA with ADC sample rates up to 250 KSps If the capabilities of a Texas Instruments TMS320C6000 DSP processor are required, an ORS-11x board can be fitted as a daughtercard to a TMS320C6000-based micro-line embedded DSPFPGA board ultra-compactThe ultra-compact UC1394a-1 and UC1394a-3 multi-chip modules provide Texas Instruments TMS320C5000 DSP, Spartan-II or Spartan-3 FPGA, and ready-to-use IEEE1394a FireWire communication capabilities in tiny 30 mm x 36 mm surface-mount PLCC packages () They are suitable as user-programmable DSPFPGA resources or as FireWire connectivity devices The UC1394a-1 incorporates a TMS320C5509 integer DSP, a 50 kGate Spartan-II FPGA, 8 MB of SDRAM In addition to the IO capabilities of the UC1394a-3, the UC1394a-1 provides external access to USB and four AD inputs provided by the TMS320C5509 DSP processor C32CPUA DSP resource board with a TMS320C32 DSP processor and SRAM, FLASH ROM, and the micro-line bus interface () Used as a modular component in the micro-line DSP product family, which allows DSP processor, data acquisition, and IEEE 1394 (FireWire) communications modules to be combined and used together for industrial embedded DSP applications 405060 MHz TMS320C32 32-bit Floating Point DSP Processor Up to 2 Mbytes of zero-wait-state RAM or Double Low Power RAM A family of low-cost embedded DSP board configurations () TMS320C6000 DSP processor 400 Mbitsec IEEE 1394 (FireWire) communications Open architecture design with off-the-shelf and OEM data acquisition and IO options The micro-line series of embedded DSPFPGA boards provides embedded systems developers with a tightly integrated suite of programmable DSP, FPGA, and IO resources in small, stand-alone capable board formats () C6713Compact Features: 300 MHz TMS320C6713 floating-point DSP Spartan 6 (LX45, LX75, LX100 or LX150) or Virtex-II (250-kGate 500kGate, or 1MGate) FPGA up to 160 configurable digital IO pins Up to 128 MB SDRAM 8 MB fl ash ROM for DSP and FPGA boot code, as well as non-voltatile parameterdata storage Onboard 400 Mbps IEEE1394a FireWire interface RS-232 interface External access to TMS320C6713 DSP IO interfaces: 32-bit EMIF, XF01 pins, Timer inputoutput pins, McASP and McBSP ports, I2C, and HPI 120 mm x 67 mm footprintISO9001:2000 accredited production and CE certification C6713CPU Features: 300 MHz TMS320C6713 floating-point DSP 400K gate or 1M gate Spartan-3 FPGA up to 96 configurable digital IO pins 64 MB SDRAM 2 MB fl ash ROM for DSP and FPGA boot code, as well as non-voltatile parameterdata storage RS-232 interface External access to TMS320C6713 DSP IO interfaces: 32-bit EMIF, XF01 pins, Timer inputoutput pins, McASP and McBSP ports, I2C, and HPI 98 mm x 67 mm footprint ISO9001:2000 accredited production and CE certification . The micro-line series of embedded DSPFPGA boards provides embedded systems developers with a tightly integrated suite of programmable DSP, FPGA, and IO resources in small, stand-alone capable board formats. () C6412Compact Features: 720 MHz TMS320C6412 integer DSP 1M gate or 4M gate Spartan-3 FPGA up to 211 configurable IO pins Up to 128 MB SDRAM Up to 32 MB fl ash ROM for DSP and FPGA boot code, as well as non-voltatile parameterdata storage Two independent IEEE1394a FireWire interfaces for streaming data inout simultaneously 10100BASE-Tx Ethernet interface USB 2.0 and RS-232 interfaces External access to DSP Processor IO interfaces: 64-bit EMIF, XF01 pins, Timer inputoutput pins, McBSP ports, I2C, and 16-32-bit HPI 120 mm x 72 mm footprint ISO9001:2000 accredited production and CE certification C641xCPU Features: 400 MHz TMS320C6410, 500MHz TMS320C6413 or 500 MHz TMS320C6418 integer DSP 500K gate, 1.2M gate, or 1.6M gate density Xilinx Spartan8482-3E FPGA: up to 98 configurable digital IO pins Up to 64 MB SDRAM 8 MB fl ash ROM for DSP and FPGA boot code, as well as non-voltatile parameterdata storage RS-232 interface External access to DSP Procesor IO interfaces: 32-bit EMIF, XF01 pins, Timer inputoutput pins, McASP and McBSP ports, I2C, and HPI 98 mm x 67 mm footprint ISO9001:2000 accredited production and CE certification . XpressDSP-compliant TCPIP protocol stack with integrated DMA support () Easy-to-use software package that enables Ethernet and Internet communications on a wide variety of TI DSP hardware platforms: Commercial off-the-shelf hardware (micro-line embedded DSP boards) Texas Instruments development starter kits custom-designed hardware incorporating TI DSPs High communication efficiency and throughput Graphical development tools compliant with applicable Internet standards micro-line C671xProvides embedded systems developers with a tightly integrated suite of programmable DSP, FPGA, and IO resources in small, stand-alone capable board formats () Target high-performance floating-point DSP applications, using the powerful Texas Instruments TMS320C6713 DSP Incorporates up to 64 MB SDRAM, 8 MB boot program flash ROM, and an onboard, high-density 250 kGate, 500 kGate, or 1 MGate Virtex-II FPGA (optionally programmable) The FPGA greatly expands processing as well as hardware interfacing possibilities A DSP board with onboard FPGA () Texas Instruments TMS320C6713 floating-point DSP processor at 225 MHz (up to 1800 MIPS or 1350 MFLOPS) Virtex-II FPGA (250k, 500k, or 1M gates) Dual 400 Mbitssec IEEE 1394 FireWire ports C6x11CPUA DSP resource board that combines either a fixed point TMS320C6211 or a floating point TMS320C6711 DSP Processor with SBSRAM, SDRAM, FLASH ROM, and the micro-line bus interface () Operating with the 32-bit fixed-point or floating-point TMS320C6211-150167 MHz or TMS320C6711-100150 MHz Micro-line bus, pin-compatible with the entire micro-line family Maximum performance of 1336 MIPS (C6211) or 900 MFLOPS (C6711) High-quality, single-board solution for applications requiring an embedded DSP and optionally programmable FPGA () Texas Instruments TMS320C6713 DSP 64 MB of SDRAM (128 MB SDRAM available on request), 2 MB flash ROM Optionally programmable Spartan-3 FPGA (up to 1 M gate density) Embedded DSP board () Texas Instruments TMS320C6211 or TMS320C6711 DSP Up to 2 MB of SDRAM or up to 64 MB of SDRAM Up to 512 KB flash EPROM, McBSP, and RS-232 micro-line C6x11CPUTexas Instruments TMS320C6211 or TMS320C6711 DSP () Up to 2 MB of SBRAM or up to 64 MB of SDRAM Up to 512 KB Flash EPROM, McBSP, and RS-232 Optional FireWire, Ethernet, analog and digital IO Micro-line C6713CompactStandalone and embedded-capable DSPFPGA board () Texas Instruments TMS320C6713 floating point DSP Processor 250k, 500, or 1M-gate complexity Virtex-II FPGA 400 MBps IEEE 1394 FireWire interface Standalone and embeddable DSPFPGA board () Texas Instruments TMS320C6713 floating point DSP 250 k, 500 k, or 1 M-gate complexity Virtex-II FPGA 400 Mbps IEEE 1394a FireWire interface A PCI-based FFT processor mezzanine that provides a complete development and processing platform for FFT-based DSP algorithms using DSP Architectures DSP-24 10,000 MIPS Vector DSP () An FFT processing module that provides high performance real-time FFT-based DSP algorithms () VectorWare is a software development tool for Vector-DSP-based boards () Provides all the tools to develop, simulatedebug, and deploy vector-DSP application code VectorBuilder is an optimizing compiler that generates vector microcode for the VT-5000 family of vector-DSP-based products Accepts a high-level vector instruction language known as VectorCode The VT-1420 product family consists of four products, VT-1420, VT-1423, VT-1425 and VT-1426 () The VT-1420 and VT-1426 are dual processor PMC modules and the VT-1423 and VT-1425 are single processor PMC modules All modules are targeted for DSP applications and are available with TMS320C6415 processors or TMS320C6416 processors These modules are compatible with any carrier board with a PMC compliant module site A 20,000 MIPS vector processing board that performs a 1K pt complex FFT in 21 181sec () The board is based on the 24-bit DSP-24 chip from DSP Architectures Designed for high-end market where FFT performance and data IO are important . A set of DSP PMC modules () VT-1420 dual and VT-1423 single TMS320C641516 DSP One or two TMS320C6415 or TMS320C6416 processors each with: clock speeds of up to 720 MHz 0, 16, 32, or 64 Mbytes of SDRAM 0, 1, or 2 Mbytes of FLASH Utopia level II interface on P14 An embedded VoIP gateway bridging legacy VME communications equipment to voicedata packet networks () 6U, single-slot, single-blade VMEbus configuration Offers modular feature expansion, scaling from a base T1E1J1 network interface board to a complete VoIP Media Gateway by adding DSP processor and protocol modules A DSP developers kit () Supports driver development for operating systems that are not directly supported by Voiceboard Includes source code for McBSP and API drivers, DSP software load utilities, API for remote IP or CompactPCI and VME based messaging and payload data transfer, example and test code, user manual, How to Write a MediaPro Device Driver manual, and up to 20 hours of telephone access to Device Driver technical support group . PTMC41PTMC41, a 240-port PTMC 2.15 DSP resource board, supported by Voiceboards broad range of off-the-shelf communications and VoIP media gateway software () DSP software libraries available for the PTMC41 include VoIP, conferencing (64 to 1,024 party), telephony functions, FAX, modems, vocoders, and RecordPlay resources For those customers desiring to integrate their own code onto the PTMC41 DSPs, Voiceboard offers a DSP Software Development Kit (SDK) including commonly needed telephony functions Will work with CPU, carrier board, or custom board that supports industry standard PICMG 2.15 PTMC specifications MediaPro resource software modules () MediaPro DSP software is downloaded into the memory of MediaPro DSP hardware Provides high-performance multi-port embedded modems and FAX servers . A high-density VME64 DSP resource board () SCSA TDM access Real-time multiprocessing of communications media datastreams Detection and generation of communications signaling tones PTMC41DSP PMC Mezzanine BoardA PTMC DSP resource board () Provides media conversion on 240 ports Flexible access to the H.110 backplane TDM bus and the carrier boards local PCI bus Real-time multiprocessing of communications media datastreams The SuperSpan VS32 is a VME 64 bus interface, software selectable T1E1J1 digital telephony network controller on a 6U board () A dual software selectable T1E1J1 span configurations, dual 100baseT connections, hot swappable, dual PTMC sites for optional DSP PMC and additional PowerPC 500 MIPS processor. The VS32 high-density dual span provides 60-port channel capacity Capabilities include play, record, call signaling tones, fax, V.22 and V.90 modem, conferencing, and VoIP packet voice through DSP PMC option SCSA backplane provides low latency switching of TDM data A DSP resource board with SCSA-bus-accessable DSP resources () Available with 24 C52 or 20 C549 fixed-point DSPs 128-Kbyte 15nsec SRAM per processor 16 Mbytes of shared DSP cache memory common to all DSPs A 240-port 6300 MIPS, DSP PMC board () Provides a full 240-port capacity for VoIP, telephony functions, T.38 Fax, V.22, V.90 modem, conferencing, or VoATM applications, including G.711 or G.723.1, G.729A, G.726 compression algorithms and G.168 long tail echo cancellation Compliant with PICMG 2.15 PTMC specifications, including access to the carrier board PCI and H.110 TDM buses 350-MIPS PowerPC 8240 executive controller supporting resource management, messaging, data buffers, TCP-UDPIP stacks, and dual redundant 100Base-T Ethernet ports The SuperSpan VS34 is a VME 64 bus interface, software selectable T1E1J1 digital telephony network controller on a 6U board () A Quad software selectable T1E1J1 span configurations, dual 100baseT connections, hot swappable, dual PTMC sites for optional DSP PMC and additional PowerPC 500 MIPS processor. The VS34 high-density dual span provides 120-port channel capacity Capabilities include play, record, call signaling tones, fax, V.22 and V.90 modem, conferencing, and VoIP packet voice through DSP PMC option SCSA backplane provides low latency switching of TDM data Conference software C5441 DSP () Getting all the processing performance, memory and high-speed IO is a never ending quest for applications heavy in digital signal processing () Integrating the flexibility of programmable logic makes building a processor even more challenging The Xilinx Virtex-5 SXT platform establishes an industry record for DSP performance delivering 352 GMACs at 550MHz, while consuming 35 percent less dynamic power as compared to previous 90nm generation devices, and is the first DSP-optimized FPGA family to integrate serial transceivers The Virtex-5 SXT platform delivers the highest ratio of DSP blocks-to-logic needed for high-performance digital signal processing applications in wireless, such as WIMAX and high-definition video, such as surveillance and broadcast Avnet Virtex-6 FPGA DSP KitWireless, aerospace and defense, instrumentation and medical imaging applications continue to drive demanding performance requirements for todays sophisticated electronic systems () Due to their inherent hardware structure advantages, Xilinx FPGAs outstrip the high-end computing power of traditional digital signal processors Based on the performance leading Virtex-6 FPGAs, this DSP Kit bundles pre-validated software tools, IP and hardware into a platform that addresses even the most challenging applications With the addition of targeted reference designs, the Virtex-6 FPGA DSP kit enables users to focus on creating their own unique differentiation from the very beginning of the product development process, accelerating development for experienced users while also simplifying the adoption of FPGAs for new users Xilinx ISE Design Suite 11Logic, system, embedded and DSP domain-specific solutions () PlanAhead8482 Design Analysis tool for optimizing performance ChipScope8482 Pro Analyzer and Serial IO Toolkit for real-time debug and verification System Generator for DSP for developing high-performance DSP systems using MathWorks products Avnet Spartan-6 FPGA DSP KitXilinx FPGAs exceed the computing power of DSPs with their inherent parallelism and offer co-processing methods of performance acceleration for signal processing () The Xilinx Spartan-6 FPGA DSP Kit integrates hardware, IP, software development tools and methodologies together into solutions that accelerate development for experienced users and simplify the adoption of FPGAs for new users With the addition of targeted reference designs, these DSP platforms enable users to focus on creating their own unique differentiation from the very beginning of the product development process This kit includes the Xilinx Spartan-6 LX150T board and allows users to quickly learn the different tool flows and design techniques involved in creating DSP centric designs with the Spartan-6 FPGA family Virtex-6 FPGA DSP KitProvides a platform for next generation products that include digital signal processing (DSP) which need to deliver more performance and flexibility with shorter development cycles and less cost and power () Out-of-the-box development solution that quickly builds confidence in developing DSP applications on FPGAs Includes a Xilinx ML605 development board including a Virtex-6 LX240T FPGA, design tools, IP, reference designs, and documentation Supports both traditional RTL and high-level design methodologies and can easily extended to include additional high-level design flows and IO daughter cards through third party partners and standardized integration . An ideal hardware platform to evaluate Xilinx FPGA in a wide range of video and imaging applications () Fully integrated and supported by the Xilinx System Generator for DSP software Utilizes high speed Ethernet hardware cosimulation capability and enables system integration, development, and verification of codecs, IP, and video algorithms in real time Comprised of a limited edition of the System Generator for DSP, Integrated Software Environment (ISE) FPGA design tool, Xilinx ML402-SX35 development board, video IO daughter card (VIODC), CMOS image sensor camera, power supply, cables, and detailed user guide and reference designs ISE Design Suite 12 software unlocks greater design productivity with breakthrough technologies for power optimization and cost () The Design Suite enables the fastest time to design completion with Xilinx Targeted Design Platforms 8211 available in four configurations aligned to user-preferred methodology logic, embedded, DSP, or system design Xilinx Targeted Design Platforms provide embedded, DSP, and hardware designers with access to an array of devices supported by open standards, common design flows, IP, and runtime platforms The ISE Design Suite offers domain-specific design environments and enables designers to meet power and performance goals with Xilinx CPLDs and FPGAs, including the new Virtex-6 and Spartan-6 families Spartan-3A DSPA DSP platform family () Xilinx XtremeDSP slice can be interconnected in creative ways on-chip Highest-performing family member provides 2,200 Gbps memory bandwidth Chips DSP48A slices can realize wide math functions, DSP filters, and complex arithmetic 8211 all at reduced power XtremeDSP DevicesThe Xilinx XtremeDSP initiative helps you develop tailored high performance DSP solutions for aerospace and defense, digital communications, multimedia, video, and imaging industries. () High-performance configurable FPGAs for DSP designs Development boards and Intellectual Property (IP) System Generator and AccelDSP design and development tools XtremeDSP SolutionStart designing using Simulink, MATLAB, or VHDL () HDLbitstream using System Generator for DSP tool Fast, parameterizable FFTs, filters, and FEC cores Free DSP software and IP core evaluations The Kintex8482-7 FPGA DSP Kit includes development boards, IO daughter cards, design tools, and reference designs, and gives designers the industry8217s largest portfolio of DSP, video, and floating-point IP blocks. () Hardware and documentation: KC705 base board with the Kintex-7 XC7K325T-FF900-2 FPGA 4DSP FMC150 high-speed ADCDAC FMC module USB, Ethernet, and MMCX RF coax cables universal power supply Downloadable schematics, BOM, and design files Documentation, including Getting Started Guide Software and IP: Full-seat ISE174 Design Suite Logic Edition, device-locked for the XC7K325T-FF900-2 FPGA CoreGen IP MathWorks174 evaluation software (MATLAB and Simulink) Targeted reference designs and tutorials Getting Started Reference Design High-performance DSP reference design . One integrated front-to-back FPGA IP catalog and design tool suite with unified interoperability () Domain specific design capture for DSP, embedded and logical design Accelerated system development via customization and integrated libraries of optimized IP Design tools optimized to minimize area while maximizing performance for Virtex-5 and Spartan-3 family Platform FPGAs Virtex-4 FPGAs for highest performance DSP () Up to 512, 500 MHz XtremeDSP Slices (18 x 18 multiply, 48-bit add) Virtex-4 for lowest power per channel 8211 each XtremeDSP Slice consumes only 2.3 mW per 100 MHz XtremeDSP Development ToolsModel and design your system using MATLAB, Simulink, and blocksets from The MathWorks () Use the Xilinx bit and cycle accurate library for designing algorithms for the FPGA Import MATLAB algorithms like linear algebra and matrix inversion and multiplication Automatically generate HDL or a bitstream at the push of a button with no loss in performance over designs written in HDL Power supply 100-240 V, 5060 Hz with universal plug adaptors USB Platform download cable for configuration and debug System Generator for DSP design softwareSSP to DSP Cookie Syncing Explained The matching process of the SSP cookie ID to the DSP cookie ID happens through a parallel process to serving ads called cookie syncing. A cookie sync is necessary because as a standard security process, web servers of any kind can only request cookies that are set to their own domain. Since the SSP sits between the end-user and all the DSP bidders in a real-time auction however, the DSP needs a way to identify the users it is looking for. Why Cookie Syncing is Necessary So lets take a simple example on a store trying to retarget their users. Lets say that you run storeABC, and user123 drops in and adds a pair of 150 shoes to their shopping cart, but never makes it to the checkout. You want to retarget that user and serve them an ad directing them back to your store to try and close the sale. Since you work with DSP456, you have a 11 pixel sitting on your shopping cart page, which forces the user to call out to DSP456s web server as they load the shopping cart page, giving DSP456 a chance to drop a cookie on user123. That cookie ID is DSPcookie789. Now, user123 is surfing around the web, and lands on awesomesite, which is using SSP123 to monetize their ad inventory. awesomesite serves a 3rd party redirect to SSP123, which drops a cookie on user123. That cookie ID is SSPcookieXYZ. SSP123 now requests a bid from DSP456 among other bidders for the impression that SSPcookieXYZ is about to view. But wait, how does DSP456 know that SSPcookieXYZ DSPcookie789 On this first ad, it doesnt, so your DSP doesnt bid on the impression. Bummer. Remember, the SSP can only read and pass its own cookie ID to bidders. Piggyback Scripts Power Cookie Syncs After SSP123 selects a winning bidder though, it runs one last piece of javascript that forces user123 to call out to a handful of regular bidders, including DSP456. In that redirect, using a query string, the SSP passes its cookie ID on user123 (SSPcookieXYZ). Now the user IS calling DSP456s web server and the DSP can request its own cookie from user123 in a process the industry refers to as piggybacking. Eureka SSPcookieXYZ also has DSPcookie789 8211 it8217s user123 The DSP knows the SSPs cookie ID because of the query string in the piggyback call, and it can read its own cookie ID because that user called its web server as the end destination with the piggyback call. DSP456 now writes into its database that DSPcookie789 SSPcookieXYZ for bid requests from SSP123. The next time user123 hits a page that SSP123 is helping to monetize, DSP456 will know it is the same user that abandoned their shopping cart and can bid appropriately. The process repeats for sites using other SSPs. It sounds complex, but all it means is that for every ad served through RTB, about 10x as many technology companies are involved in the cookie-sync process. The reason the syncing process occurs after the auction happens and not before it is because of latency and user experience. If user123 had to call 10 DSPs, wait for those DSPs to cookie their machine, write the matching SSP id into their database, and then bid, it would dramatically slow down the entire auction process for everyone. If the cookie sync fails on the other hand, well there will be many more opportunities for that. Cookie Syncing Step-by-Step Below is a simplified diagram of the cookie sync process, where user123 visits the Marketer8217s website first (1), is then redirected to the Marketer8217s DSP (2), calls the Marketer8217s DSP (3), receives the DSP8217s cookie (4) and is simultaneously redirected to various SSPs that the DSP is cookie syncing with (5). When the user calls those SSPs, the call passes DSP4568217s cookie ID on that user in a key value parameter. The process completes when the DSP4568217s ID is logged in the match table for each SSP, and receives the SSP8217s cookie in return. As an interesting post-script to this, the SSP might redirect the user back to DSP if the DSP is hosting the match table instead of the SSP. This would be the same process as 4 5, just in the reverse order, with the SSP passing its ID to the DSP so the DSP can log both IDs in its own match table. Who hosts the match table is a commercial arrangement that DSPs and SSPs Exchanges make with each other, with the match table host typically paid to shoulder the cost of maintaining the database. Example Cookie Sync Scripts If you are interested, here are the URLs that run the piggyback script for each major SSP 8211 these pages look blank, so you8217ll have to 8216view source8217 to see the code. Pubmatic: ads. pubmaticAdServerjssyncuppixels. html It looks as though 8216vcode8217 is the item passing the cookie ID. Rubicon Project: tap2-cdn. rubiconprojectpartnerscriptsrubiconemily. html It looks as though 8216nid8217 is the item passing the cookie ID. Post navigation Great article Ben. I8217m interested in knowing a couple of things: Firstly, could you answer Clive Page8217s question, which i have reprinted below 8221 Clive Page September 11, 2012 at 4:48 am Hi Ben, What other information can be passed via an SSP ID to the DSP to add value in the bidding process. From your description, the cookie syncing only supports a binary decision from the DSP as to whether or not there is a DSP cookie on the users machine yes or no. It is commonly referenced within the industry that publishers have a wealth of data points on their users, and the onus should be on the publishers to expose this data with a view to better monetizing their sites. With the above definition, all of the information used as the basis for the bidding decision is on the advertiser side through the retargeting pixel. Is there any other information that can be passed via the SSP cookie which would give the bidders greater insight into the user and their behaviour, so for example the segment IDs (and segment definitions) to which the user belongs as classified by the publisher or the SSP.8221 Secondly, I want to know that if I am a publisher, what technology do i need to have on my website to be part track all the information that i can give to an SSP. Do i just need to have a pixel or drop a cookie on every user that visits my website or do i have to allow the SSP to drop it8217s cookies on the users that visit my website Also, is there any information i can withold or would the SSP have access to all the information on my website once they place their trackers Finally, is there any way I can also get access to the SSP8217s cookie pool, if I want to advertise to new users that have been to other relevantcompeting websites Not sure how I missed that one 8211 in terms of passing data to the DSP, there8217s lots of ways to do that, but it8217s a separate process from cookie syncing. Rather, you8217d do this in the bid request. I8217d recommend you take a look at sections 3.2.15 thru 3.2.17 of the OpenRTB 2.4 spec here: iabwp-contentuploads201601OpenRTB-API-Specification-Version-2-4-DRAFT. pdf There are dedicated and predefined keyvalues for age and gender, as well as a generic keyvalue parameter the publisher could use to pass whatever information it wanted. This also allows for segment data to be passed. That said, in practice I would say these keys are rarely ever used for a few reasons. First, advertisers don8217t need publisher to pass them 3rd party data sets, as the advertiser can integrate with those themselves, and for likely a better rate since they are a buyer. Secondly, if a publisher has valuable 1st party data they want to make available to buyers, they8217ll typically do that through setting up a deal ID, which will stand in place for perhaps a host of data elements. By using a deal ID, it allows the publisher to more easily control the commercial terms of using that data, and to clearly explain what the data means, where it comes from, and so forth which the buyer might not understand if it was simply present in the request. This is covered in section 3.2.20. To your second question, you may need to pass additional information to the SSP if you want to add data to your bid requests. Certainly you8217d need the SSP8217s tag on page, but you might also need some JavaScript to pick up your content section ID for example, or pass user information. Then, you8217d typically setup a deal ID in your SSP8217s UI based on the data you8217re passing over to it. There8217s no other special technology you need per se, though if you wanted to pass user data it could benefit you to have a data management platform. Your SSP would only have access to the information you choose to pass it, though you would want to pay attention to your transparency settings on how you are represented to buyers on the exchange. What I mean is, if your site URLs are always structured as harryswebsitecontentsectionID, then if you pass the full ID it might not be very difficult for a buyer to target just one content section vs. another, and that will work against you if you are trying to create separate and premium deals for each content section. To your third question, typically no 8211 you might be able to use a DSP for this purpose. You8217d have to buy media on those competitor sites first, then you could retarget them on other sites. This could be difficult though if your competitors are blocking you, which they are likely to do. The SSP DSP wouldn8217t maintain data segments that were so specific as 8220user went to X domain8221 that I would imagine they8217d make available to you. Hope that helps 8211 Ben Firstly, great article and thanks for all the speedy and detailed responses. I have a couple of basic questions about cookies and cookie syncing 1) As an advertiser, can I use my 1st party cookie to tracking browsing behavior of my website visitors outside my website If yes, can I use this to create rich user profiles and then send them more targeted messages on owned media If not, how can 3rd party cookies track such browsing 2) How do 3rd party data providers such as Eyota or Lotame cookie sync with Ad exchanges DSP8217s Is there some piggybacking at the end of the script they use to drop a cookie to the user8217s browsers via major publishers Thanks 8211 will try to help. 1. Yes, assuming you buy media on those other websites. That is, your 1st party cookie is set on the user8217s device, and because it can only be read by your server, you need that user to make a request to your server from those other websites. The easiest way to practically do that is to run a retargeting media campaign against those users, serve them an ad, and force them to call your website in the process through a tracking pixel. You can then use this information to further segment 038 target users. 3rd party cookies essentially track users for 8220free8221 because someone else is paying for the media, or they are part of the transaction process. 2. Yes, they compel users to execute a cookie sync with exchanges DSPs as part of their core JavaScript, commonly called a piggyback script. The DSPs Exchanges could also kick off the cookie syncing process on their end through the same process. Hope that helps 8211 Leave a Reply Cancel replySSP to DSP Cookie Syncing Explained The matching process of the SSP cookie ID to the DSP cookie ID happens through a parallel process to serving ads called cookie syncing. A cookie sync is necessary because as a standard security process, web servers of any kind can only request cookies that are set to their own domain. Since the SSP sits between the end-user and all the DSP bidders in a real-time auction however, the DSP needs a way to identify the users it is looking for. Why Cookie Syncing is Necessary So lets take a simple example on a store trying to retarget their users. Lets say that you run storeABC, and user123 drops in and adds a pair of 150 shoes to their shopping cart, but never makes it to the checkout. You want to retarget that user and serve them an ad directing them back to your store to try and close the sale. Since you work with DSP456, you have a 11 pixel sitting on your shopping cart page, which forces the user to call out to DSP456s web server as they load the shopping cart page, giving DSP456 a chance to drop a cookie on user123. That cookie ID is DSPcookie789. Now, user123 is surfing around the web, and lands on awesomesite, which is using SSP123 to monetize their ad inventory. awesomesite serves a 3rd party redirect to SSP123, which drops a cookie on user123. That cookie ID is SSPcookieXYZ. SSP123 now requests a bid from DSP456 among other bidders for the impression that SSPcookieXYZ is about to view. But wait, how does DSP456 know that SSPcookieXYZ DSPcookie789 On this first ad, it doesnt, so your DSP doesnt bid on the impression. Bummer. Remember, the SSP can only read and pass its own cookie ID to bidders. Piggyback Scripts Power Cookie Syncs After SSP123 selects a winning bidder though, it runs one last piece of javascript that forces user123 to call out to a handful of regular bidders, including DSP456. In that redirect, using a query string, the SSP passes its cookie ID on user123 (SSPcookieXYZ). Now the user IS calling DSP456s web server and the DSP can request its own cookie from user123 in a process the industry refers to as piggybacking. Eureka SSPcookieXYZ also has DSPcookie789 8211 it8217s user123 The DSP knows the SSPs cookie ID because of the query string in the piggyback call, and it can read its own cookie ID because that user called its web server as the end destination with the piggyback call. DSP456 now writes into its database that DSPcookie789 SSPcookieXYZ for bid requests from SSP123. The next time user123 hits a page that SSP123 is helping to monetize, DSP456 will know it is the same user that abandoned their shopping cart and can bid appropriately. The process repeats for sites using other SSPs. It sounds complex, but all it means is that for every ad served through RTB, about 10x as many technology companies are involved in the cookie-sync process. The reason the syncing process occurs after the auction happens and not before it is because of latency and user experience. If user123 had to call 10 DSPs, wait for those DSPs to cookie their machine, write the matching SSP id into their database, and then bid, it would dramatically slow down the entire auction process for everyone. If the cookie sync fails on the other hand, well there will be many more opportunities for that. Cookie Syncing Step-by-Step Below is a simplified diagram of the cookie sync process, where user123 visits the Marketer8217s website first (1), is then redirected to the Marketer8217s DSP (2), calls the Marketer8217s DSP (3), receives the DSP8217s cookie (4) and is simultaneously redirected to various SSPs that the DSP is cookie syncing with (5). When the user calls those SSPs, the call passes DSP4568217s cookie ID on that user in a key value parameter. The process completes when the DSP4568217s ID is logged in the match table for each SSP, and receives the SSP8217s cookie in return. As an interesting post-script to this, the SSP might redirect the user back to DSP if the DSP is hosting the match table instead of the SSP. This would be the same process as 4 5, just in the reverse order, with the SSP passing its ID to the DSP so the DSP can log both IDs in its own match table. Who hosts the match table is a commercial arrangement that DSPs and SSPs Exchanges make with each other, with the match table host typically paid to shoulder the cost of maintaining the database. Example Cookie Sync Scripts If you are interested, here are the URLs that run the piggyback script for each major SSP 8211 these pages look blank, so you8217ll have to 8216view source8217 to see the code. Pubmatic: ads. pubmaticAdServerjssyncuppixels. html It looks as though 8216vcode8217 is the item passing the cookie ID. Rubicon Project: tap2-cdn. rubiconprojectpartnerscriptsrubiconemily. html It looks as though 8216nid8217 is the item passing the cookie ID. Post navigation Great article Ben. I8217m interested in knowing a couple of things: Firstly, could you answer Clive Page8217s question, which i have reprinted below 8221 Clive Page September 11, 2012 at 4:48 am Hi Ben, What other information can be passed via an SSP ID to the DSP to add value in the bidding process. From your description, the cookie syncing only supports a binary decision from the DSP as to whether or not there is a DSP cookie on the users machine yes or no. It is commonly referenced within the industry that publishers have a wealth of data points on their users, and the onus should be on the publishers to expose this data with a view to better monetizing their sites. With the above definition, all of the information used as the basis for the bidding decision is on the advertiser side through the retargeting pixel. Is there any other information that can be passed via the SSP cookie which would give the bidders greater insight into the user and their behaviour, so for example the segment IDs (and segment definitions) to which the user belongs as classified by the publisher or the SSP.8221 Secondly, I want to know that if I am a publisher, what technology do i need to have on my website to be part track all the information that i can give to an SSP. Do i just need to have a pixel or drop a cookie on every user that visits my website or do i have to allow the SSP to drop it8217s cookies on the users that visit my website Also, is there any information i can withold or would the SSP have access to all the information on my website once they place their trackers Finally, is there any way I can also get access to the SSP8217s cookie pool, if I want to advertise to new users that have been to other relevantcompeting websites Not sure how I missed that one 8211 in terms of passing data to the DSP, there8217s lots of ways to do that, but it8217s a separate process from cookie syncing. Rather, you8217d do this in the bid request. I8217d recommend you take a look at sections 3.2.15 thru 3.2.17 of the OpenRTB 2.4 spec here: iabwp-contentuploads201601OpenRTB-API-Specification-Version-2-4-DRAFT. pdf There are dedicated and predefined keyvalues for age and gender, as well as a generic keyvalue parameter the publisher could use to pass whatever information it wanted. This also allows for segment data to be passed. That said, in practice I would say these keys are rarely ever used for a few reasons. First, advertisers don8217t need publisher to pass them 3rd party data sets, as the advertiser can integrate with those themselves, and for likely a better rate since they are a buyer. Secondly, if a publisher has valuable 1st party data they want to make available to buyers, they8217ll typically do that through setting up a deal ID, which will stand in place for perhaps a host of data elements. By using a deal ID, it allows the publisher to more easily control the commercial terms of using that data, and to clearly explain what the data means, where it comes from, and so forth which the buyer might not understand if it was simply present in the request. This is covered in section 3.2.20. To your second question, you may need to pass additional information to the SSP if you want to add data to your bid requests. Certainly you8217d need the SSP8217s tag on page, but you might also need some JavaScript to pick up your content section ID for example, or pass user information. Then, you8217d typically setup a deal ID in your SSP8217s UI based on the data you8217re passing over to it. There8217s no other special technology you need per se, though if you wanted to pass user data it could benefit you to have a data management platform. Your SSP would only have access to the information you choose to pass it, though you would want to pay attention to your transparency settings on how you are represented to buyers on the exchange. What I mean is, if your site URLs are always structured as harryswebsitecontentsectionID, then if you pass the full ID it might not be very difficult for a buyer to target just one content section vs. another, and that will work against you if you are trying to create separate and premium deals for each content section. To your third question, typically no 8211 you might be able to use a DSP for this purpose. You8217d have to buy media on those competitor sites first, then you could retarget them on other sites. This could be difficult though if your competitors are blocking you, which they are likely to do. The SSP DSP wouldn8217t maintain data segments that were so specific as 8220user went to X domain8221 that I would imagine they8217d make available to you. Hope that helps 8211 Ben Firstly, great article and thanks for all the speedy and detailed responses. I have a couple of basic questions about cookies and cookie syncing 1) As an advertiser, can I use my 1st party cookie to tracking browsing behavior of my website visitors outside my website If yes, can I use this to create rich user profiles and then send them more targeted messages on owned media If not, how can 3rd party cookies track such browsing 2) How do 3rd party data providers such as Eyota or Lotame cookie sync with Ad exchanges DSP8217s Is there some piggybacking at the end of the script they use to drop a cookie to the user8217s browsers via major publishers Thanks 8211 will try to help. 1. Yes, assuming you buy media on those other websites. That is, your 1st party cookie is set on the user8217s device, and because it can only be read by your server, you need that user to make a request to your server from those other websites. The easiest way to practically do that is to run a retargeting media campaign against those users, serve them an ad, and force them to call your website in the process through a tracking pixel. You can then use this information to further segment 038 target users. 3rd party cookies essentially track users for 8220free8221 because someone else is paying for the media, or they are part of the transaction process. 2. Yes, they compel users to execute a cookie sync with exchanges DSPs as part of their core JavaScript, commonly called a piggyback script. The DSPs Exchanges could also kick off the cookie syncing process on their end through the same process. Hope that helps 8211 Leave a Reply Cancel reply